
 THE EISA BUS EXTENSION.

  The EISA (Enhanced Industry Standard Architecture) came out as
  a response to IBM's MicroChannel Bus from a consortium of
  computer manufacturers.

  While MicroChannel was designed as a revolutionary (and downward
  incompatible) bus , EISA was designed with the main aim of AT
  Bus compatibility: every board designed for AT Bus systems could
  be used on an EISA system.

  The first problem that EISA consortium had to tackle with was the
  loose timing specification for the ISA bus.

  Timings for PC,XT and AT mainboards were never specified by IBM
  but EISA needed some firmly defined specification to meet its
  purpose : AT Bus extension with downward compatibility.

  Then , the second important problem that EISA designers met ,
  was the different bus widths for the many devices available
  for the ISA bus. EISA had to settle things for 8-bit, 16-bit
  and 32-bit burst mode transfers , running at 8 or 33MHz , with
  or without wait states. Because EISA allows bus mastering, this
  key feature had to be extended to the host and any bus master
  device. The system was developed to execute accesses from :
  - the host CPU
  - a 16 bit or 32 bit EISA master
  - an ISA master
  and directed to any possible combination of five kinds of
  slaves (EISA 32 bit slaves , EISA 16 bit slaves with or
  without burst mode capabilities , ISA 16 or 8 bit slaves).

  This EISA feature was called "cycle translation".
  Cycle translation happens when the bus master and the EISA bus
  controller see that a data transfer can't be processed in one
  32-bit bus cycle (e.g. when a 32 bit EISA master communicates
  with a 8 bit ISA board). The bus master look at certain signals
  just after gaining bus control ; the assertion or negation of
  these signals specifies the kind of slave . If it's not a 32 bit
  EISA board, then the bus controller regains bus ownership and
  drives on the bus the same address and data lines driven by the
  bus master. Half a cycle later , the bus master gets off and the
  bus controller takes on the cycle. Now it performs the required
  number of ISA cycles to complete the data transfer.

  In the same way , the bus controller takes charge of the transfer
  when a 16 bit slave tries to address the upper word on a 32 bit
  EISA board. In this situation , the bus controller copies the
  word on the low order lines of the data bus to the upper lines
  ("copy up") then gains bus control and performs the transfer.

        Slave    EISA      EISA      EISA       ISA
  Master        32-bit    16-bit    16-bit
                         (burst)
  EISA 32          B        M         M          M

  EISA 16          C        B         B          M

  Intel BMIC       B        B         M          M


     B = burst mode transfer is possible
     C = bus controller performs copy-up cycles
     M = mismatch . Bus controller performs cycle translation

  EISA is designed for high performance : EISA boards can execute
  32 bit , burst mode, data transfers on a 33MBps bandwidth.

  On the ISA bus , a big problem is the little number of available
  IRQs on the expansion bus. EISA claims to resolve it by making IRQs
  shareable between EISA boards , via a level-triggered interrupt
  system . Each EISA board infact provides a set of pull-up resistors
  and open collector drivers on the IRQ lines , while ISA cards use
  edge triggered , tristate driven , IRQs.
  Due to this fact , EISA and ISA boards cannot share the same interrupt.

  The big problem of bus mastering is the priority arbitration. On the
  EISA bus , the DRAM refresh controller, the DMA channel 0 , the pending
  bus master requests gain EISA bus ownership by a rotating arbitration
  scheme . This means that no high priority requests will ever starve ,
  although can happen that a lower priority DMA channel gets starved for
  bus usage. A feature of the Intel Bus controller is the use of a watchdog
  counter to avoid that no bus master takes on the bus too much time. If
  this happens , the master is removed and a NMI is issued on the host
  CPU.

 The EISA connector is the key feature to 100% ISA card compatibility.
 Connector pins are put on two levels. The upper level carries ISA
 signals , in the same position and with the same card depth used for
 16-bit AT buses.
 The lower level carries EISA signals. Keytabs are used to prevent ISA
 cards to connect with EISA signals.

 The first EISA Bus chipset has been made by Intel and consists of three
 components :
 - Integrated System Peripheral (ISP)
 - EISA Bus Controller (EBC)
 - Bus Master Interface Chip (BMIC)

 EBC and ISP are designed to be tigthly coupled ,the BMIC is designed for
 add-on cards that need a reliable bus mastering interface for EISA.
 ISP supplies an interrupt controller , a DMA controller and some timers.
 Provides logic for counters , parity checks , three-way rotating bus
 arbitration and RAM refresh cycles.

 BMIC provides a bus master interface on intelligent expansion boards ,
 and has a local bus feature designed on the 80186 CPU. It implements
 a communication scheme between host CPU and local processor , using
 a sort of local mailbox registers,or via an interface that allows the
 host CPU to access the local address space. Is also possible to use
 the BMIC on boards without a local CPU.

 EISA BUS - EXPANSION SLOT LAYOUT


                           ___
              GND         |___|  >    IO Ch Chk
                          |___|
              Reset Drv > |___| <>    D7
              gnd         |___|       cmd-
              +5V         |___| <>    D6
              +5v         |___|       start-
              IRQ 2    <  |___| <>    D5
              +5v         |___|       exrdy
              -5V         |___| <>    D4
              mfg spec    |___|       ex32-
              DRQ 2    <  |___| <>    D3
              mfg spec    |___|       gnd
              -12V        |___| <>    D2
              key         |___|       key
              not used    |___| <>    D1
              mfg spec    |___|       ex16-
              +12V        |___| <>    D0
              +12v        |___|       slburst-
              GND         |___|  >    IO Ch Rdy
              m-io        |___|       msburst-
              SMEMW-    > |___| <     AEN
              lock-       |___|       w-r
              SMEMR-    > |___| <>    A19
              reserved    |___|       gnd
              IOW-     <> |___| <>    A18
              gnd         |___|       reserved
              IOR-     <> |___| <>    A17
              reserved    |___|       reserved
              DACK3-    > |___| <>    A16
              be3-        |___|       reserved
              DRQ3     <  |___| <>    A15
              key         |___|       key
              DACK1-    > |___| <>    A14
              be2-        |___|       be1-
              DRQ1     <  |___| <>    A13
              be0-        |___|       la31
              Refresh-  > |___| <>    A12
              gnd         |___|       gnd
              CLK       > |___| <>    A11
              +5v         |___|       la30
              IRQ7     <  |___| <>    A10
              la29        |___|       la28
              IRQ6     <  |___| <>    A9
              gnd         |___|       la27
              IRQ5     <  |___| <>    A8
              la26        |___|       la25
              IRQ4     <  |___| <>    A7
              la24        |___|       gnd
              IRQ3     <  |___| <>    A6
              key         |___|       key
              DACK2-    > |___| <>    A5
              la16        |___|       la15
              TC        > |___| <>    A4
              la14        |___|       la13
              ALE       > |___| <>    A3
              +5v         |___|       la12
              +5v         |___| <>    A2
              +5v         |___|       la11
              OSC       > |___| <>    A1
              gnd         |___|       gnd
              GND         |___| <>    A0
              la10        |___|       la9

                           ___
                          |___|
            MEM CS 16- <  |___|  <        SBHE
                la8       |___|         la7
            IO CS 16-  <  |___|  <>       LA23
                la6       |___|         gnd
            IRQ10      <  |___|  <>       LA22
                la5       |___|         la4
            IRQ11      <  |___|  <>       LA21
                +5v       |___|         la3
            IRQ12      <  |___|  <>       LA20
                la2       |___|         gnd
            IRQ15      <  |___|  <>       LA19
                key       |___|         key
            IRQ14      <  |___|  <>       LA18
                d16       |___|         d17
            DACK0-      > |___|  <>       LA17
                d18       |___|         d19
            DRQ0       <  |___|  <        MEMR-
                gnd       |___|         d20
            DACK5-      > |___|  <        MEMW-
                d21       |___|         d22
            DRQ5       <  |___|  <>       SD08
                d23       |___|         gnd
            DACK6-      > |___|  <>       SD09
                d24       |___|         d25
            DRQ6       <  |___|  <>       SD10
                gnd       |___|         d26
            DACK7-      > |___|  <>       SD11
                d27       |___|         d28
            DRQ7       <  |___|  <>       SD12
                key       |___|         key
            +5Vcc         |___|  <>       SD13
                d29       |___|         gnd
            MASTER-    <  |___|  <>       SD14
                +5v       |___|         d30
            GND           |___|  <>       SD15
                mackn-    |___|         mreqn-


 UPPERCASE = these lines are common to the ISA bus.
 lowercase = these lines are specific to the EISA standard.

 ISA bus lines are explained in the XT and AT bus documents.
 EISA signals are described below.

 BE0- , BE3-

  These signals are analogous to the BE0- , BE3- pins on the i386 and i486
  microprocessors.
  They indicate the byte on the 32 bit bus used in the bus cycle.
  BE0- indicates data lines 0 thru 7 , BE3- data lines 24 thru 31.


 M-IO

  This line is used to distinguish between EISA memory cycles and EISA I/O
  cycles.


 START-

  This signal is asserted when an EISA bus cycle starts.


 CMD-

  Is used for timing control within an EISA cycle.


 MSBURST-

  Is asserted by a bus master when it can perform burst cycles


 SLBURST-

  Is asserted by a bus slave when it can accept burst cycles


 EX32,EX16

  The first is asserted by a bus slave to indicate it is an EISA board
  that can accept 32 bit-wide transfers. The second is the same for 16 bit.
  If none is asserted , the bus uses ISA compatibility for the current cycle.


 EXRDY

  Is asserted when an EISA slave is ready to terminate a cycle.


 MREQn-

  Is asserted by the potential bus master n to request bus control.


 MACKn-

  Is asserted when bus master n got bus control.


 D16-D31

  16 new data lines. Added to ISA data lines , create a 32 bit wide bus.


 LA2-LA31

  New , unlatched , address lines. Are the EISA fast path to the peripheral
  boards. LA0 and LA1 aren't needed because BE0 -  BE3 indicate the byte lane
  used.
 
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