@C9Bit structure of ARM commands (ARM 250)

@C7
And for all of you, who

 a) don`t have the PRM`s (or a similar book)
 b) are too lazy to do it yourself
 c) want to know it anyway,

the bit structure of the ARM instruction set, without guaranty!
(Because I had no literature about this theme and had to find it out myself on
a rainy sunday...)

Above all the legend of all symbols used:

c = conditioncode:: EQ,NE,CS (HS),CC (LO),MI,PL,VS,VC,HI,LS,GE,LT,GT,LE,AL,NV
S = S-option:: off, on
P = P-option:: off, on (0,15)
B = B-option:: off, on
L = L-option:: off, on
! = !-option (Store calcualated address after STR to base address):: off,on
i = increase base address by <offset> BEFORE memory access:: off, on
^ = ^-option:: off, on
+ = sign:: minus, plus
p = operation::  register ( SHIFT number ), number
q = operation::  number, Register ( SHIFT number )
a = addressoffset | SWI-Number (24 bits)
z = number  (12 Bit) 
b = bit sequence  (8 Bit)
> = bit sequence ROR (4 Bit)
k = stack-Mode:: DA, IA, DB, IB
d = Rd (4 bits)
n = Rn (4 bits)
m = Rm (4 bits)
s = Rs (4 bits)
l = register list (16 bit: R<nr> = bit<nr> )  
r = Barrel-Shift-Mode:: LSL (ASL),LSR,ASR,ROR (RRX => vvvv v = 0000 0)
v = shift-Value (5 bits)
0 = 0
1 = 1
? = 0 (isn`t considered)
u = 0 (undefined)

Remarks:

  ASL is the same as LSL
  RRX is represented by ROR #0
  OP2 = <reg> is represented by <reg>,LSL #0
      no OP2 is represented by [Rn,#0] (only allowed in section 1)
  P   is represented by Rd = 15 (dddd = Bit 12-15)

group 0:

      flag   Command   Rn    Rd       Op2
      ====    ======  ====  ==== ===============
      
AND:: cccc 00p0  000S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn AND constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn AND (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn AND (Rm SHIFT Rs):

EOR:: cccc 00p0  001S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn EOR constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn EOR (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn EOR (Rm SHIFT Rs):

SUB:: cccc 00p0  010S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn SUB constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn SUB (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn SUB (Rm SHIFT Rs):

RSB:: cccc 00p0  011S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn RSB constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn RSB (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn RSB (Rm SHIFT Rs):

ADD:: cccc 00p0  100S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn ADD constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn ADD (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn ADD (Rm SHIFT Rs):

ADC:: cccc 00p0  101S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn ADC constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn ADC (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn ADC (Rm SHIFT Rs):

SBC:: cccc 00p0  110S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn SBC constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn SBC (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn SBC (Rm SHIFT Rs):

RSC:: cccc 00p0  111S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn RSC constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn RSC (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn RSC (Rm SHIFT Rs):

TST:: cccc 00p1  0001 nnnn  PPPP
             1                   >>>>  bbbb bbbb :Flags=Rn AND constant:
             0                   vvvv  vrr0 mmmm :Flags=Rn AND (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Flags=Rn AND (Rm SHIFT Rs):

TEQ:: cccc 00p1  0011 nnnn  PPPP
             1                   >>>>  bbbb bbbb :Flags=Rn EOR constant:
             0                   vvvv  vrr0 mmmm :Flags=Rn EOR (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Flags=Rn EOR (Rm SHIFT Rs):

CMP:: cccc 00p1  0101 nnnn  PPPP
             1                   >>>>  bbbb bbbb :Flags=Rn SUB constant:
             0                   vvvv  vrr0 mmmm :Flags=Rn SUB (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Flags=Rn SUB (Rm SHIFT Rs):

CMN:: cccc 00p1  0111 nnnn  PPPP
             1                   >>>>  bbbb bbbb :Flags=Rn SUB-constant:
             0                   vvvv  vrr0 mmmm :Flags=Rn SUB-(Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Flags=Rn SUB-(Rm SHIFT Rs):

ORR:: cccc 00p1  100S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn ORR constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn ORR (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn ORR (Rm SHIFT Rs):

MOV:: cccc 00p1  101S ????  dddd
             1                   >>>>  bbbb bbbb :Rd=constant:
             0                   vvvv  vrr0 mmmm :Rd=Rm SHIFT v:
             0                   ssss  0rr1 mmmm :Rd=Rm SHIFT Rs:

BIC:: cccc 00p1  110S nnnn  dddd
             1                   >>>>  bbbb bbbb :Rd=Rn BIC constant:
             0                   vvvv  vrr0 mmmm :Rd=Rn BIC (Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=Rn BIC (Rm SHIFT Rs):
                                 
MVN:: cccc 00p1  111S ????  dddd
             1                   >>>>  bbbb bbbb :Rd=NOT constant:
             0                   vvvv  vrr0 mmmm :Rd=NOT(Rm SHIFT v):
             0                   ssss  0rr1 mmmm :Rd=NOT(Rm SHIFT Rs):

group 0a

      flag             Rd    Rn   Rs   Com.  Rm
      ====            ====  ==== ====  ==== ====

MUL:: cccc 000u  uu0S dddd  ???? ssss  1??1 mmmm :Rd=Rm*Rs:

MLA:: cccc 000u  uu1S dddd  nnnn ssss  1??1 mmmm :Rd=Rm*Rs+Rn:

group 1

      flag Co-------m  Rn    Rd       Op2
      ==== ==       = ====  ==== ===============

STR:: cccc 01qi  +B!0 nnnn  dddd
             0                   zzzz  zzzz zzzz :Rd=>>Rn(+(-)z);Rn(+):
             1                   vvvv  vrru mmmm :Rd=>>Rn(+(-)Op2shft);Rn(+):

LDR:: cccc 01qi  +B!1 nnnn  dddd
             0                   zzzz  zzzz zzzz :Rd<<=Rn(+(-)z);Rn(+):
             1                   vvvv  vrru mmmm :Rd<<=Rn(+(-)Op2shft);Rn(+):

group 2

      flag Com------m  Rn          Rlist
      ==== ===      = ====  ====================

STM:: cccc 100k  k^!0 nnnn  llll llll  llll llll :Rlist=>>Rn;Rn(+):

LDM:: cccc 100k  k^!1 nnnn  llll llll  llll llll :Rlist<<=Rn;Rn(+):


group 2a

      flag Com             Adressoffset
      ==== ===   ===============================
      
B  :: cccc 101L  aaaa aaaa  aaaa aaaa  aaaa aaaa :PC+=a << 2:


group 3

      flag Com             SWI-Nummer
      ==== ===   ===============================
      
SWI:: cccc 1111  aaaa aaaa  aaaa aaaa  aaaa aaaa :PC -->> SWI-addr.:


Section 3a :11yy: (coprozessorcommands: yy <> 11 )

That`s all folks.

As you can see the 32 bits are nearly used up. Who has ideas for (compatible)
improvements of the ARM: Branch pipeline, 64 byte code, more registers or what?
(Don`t care about economical limits, perhaps technical ones.)

                                                                       R.Lorenz
                                       (translated into English by the editors)

