     $DE0A/56842/RR+10:  SilverSurfer: Interrupt Identification Register (read)
                                       FIFO Control Register (write)
      On read:

       +----------+--------------------------------------------------------+
       | Bit  7   |   1 = FIFO queues enabled                              |
       | Bits 6-4 |   reserved                                             |
       | Bit  3   |   1 = Timeout Interrupt pending                        |
       | Bits 2+1 |   Interrupt ID Bits:                                   |
       |          |             Meaning           |Priority   |  To reset  |
       |          |   00 = Modem Status change    | lowest    | read $DE0E |
       |          |   01 = Transmit Register empty| low       | read $DE0A/|
       |          |                               |           |write $DE08 |
       |          |   10 = Data available         | high      | read $DE08 |
       |          |   11 = Line Status            | highest   | read $DE0D |
       | Bit  0   |   0(!) = Interrupt pending                             |
       +----------+--------------------------------------------------------+

      On write:

       +----------+--------------------------------------------------------+
       | Bits 7+6 |   Trigger Level: 00,01,10,11 = 1,4,8,14 Bytes          |
       | Bits 5-4 |   reserved                                             |
       | Bit  3   |   1 = change RXRDY & TXRDY pins to DMA Mode (unused?)  |
       | Bit  2   |   1 = clear Transmit FIFO                              |
       | Bit  1   |   1 = clear Reciever FIFO                              |
       | Bit  0   |   1 = enable FIFO and clear FIFO queues                |
       +----------+--------------------------------------------------------+

       Bit 0 must be set in order to write to any other bits.

       When Bits 1 or 2 are set, the FIFO is cleared and the bit is reset.
       The corresponding shift register is not cleared.