     6510/65816 Addressing mode: Absolute (R-M-W) -- a

     (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB,SLO,SRE,RLA,RRA,ISB,DCP)
     (3 bytes)  (6 and 8 cycles)

        +---------------+------------------+-----------------------+----------+
        |     Cycle     |   Address Bus    |       Data Bus        |Read/Write|
        +---------------+------------------+-----------------------+----------+
        |           1   |  PBR,PC          | Op Code               |    R     |
        |           2   |  PBR,PC+1        | Absolute Address Low  |    R     |
        |           3   |  PBR,PC+2        | Absolute Address High |    R     |
        |           4   |  DBR,AA          | Data Low              |    R     |
        |       (1) 4a  |  DBR,AA+1        | Data High             |    R     |
        |   (12)(3) 5   |  DBR,AA+2        | Internal Operation    |    R     |
        |       (1) 6a  |  DBR,AA+1        | Data High             |    W     |
        |           6   |  DBR,AA          | Data Low              |    W     |
        +---------------+------------------+-----------------------+----------+
        (1) Add 1 cycle for M=0 or X=0 (i.e. 16 bit data).
        (3) Special case for aborting instruction. This is the last cycle which
            may be aborted or the Status, PBR or DBR registers will be updated.
       (12) Unmodified Data Low is written back to memory in 6502 emulation
            mode (E=1).

        See also: Abbreviations