     $D019/53273/VIC+25:  VIC Interrupt Request Register (IRR)

       1 = IRQ occured

       +----------+-------------------------------------------------------+
       | Bit 7    |   1 = IRQ has been generated                          |
       | Bit 3    |   Light-Pen Triggered IRQ Flag                        |
       | Bit 2    |   Sprite to Sprite Collision IRQ Flag     (see $D01E) |
       | Bit 1    |   Sprite to Background Collision IRQ Flag (see $D01F) |
       | Bit 0    |   Raster Compare IRQ Flag                 (see $D012) |
       +----------+-------------------------------------------------------+

       An IRQ will be initiated, if equal bits are set in IRR and IMR.

       Your VIC does NOT clear this register! You have to do this by
       setting the bits you want to clear.
       Note also that read-modify-write-instructions, like INC, ASL..., will
       not work on 65816-CPUs in native mode!

    Kernal-Reference:

     LDA $D019   : $FF63